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This paper gives insight in reliability of p-channel VDMOSFET power transistors subjected to NBT stressing. Effects that lead to degradation of characteristics of these electronic circuits are presented, out of which threshold voltage shift with NBT stressing is further analysed. Measurements have been done and experimental results of the threshold voltage degradation of power transistors IRF9520 caused by different types of negative bias temperature stressing are shown. Stressing types, both static and pulsed, and their impact on transistors, especially on threshold voltage shifts have been explained in more details. An elementary equivalent electrical circuit is designed and proposed with the goal to model impact of both types of stressing, and also to calculate and estimate reliability of the circuit under specified stress. All of the elements of the modeling circuit and their dependencies are explained. Example of modeling from the experimental data is given together with the comparison between measured and modeled results. Differences between obtained results are discussed.
This work has been supported by the Ministry of Education, Science and Technological Development of the Republic of Serbia under grant "Characterization, analysis, and modeling of physical phenomena in thin layers for application in MOS nanocomponents" (grant no. OI-171026) and under grant "Design, Optimization and Application of Energy Harvesting Sensor Technologies and (grant no. TR-32026). Work has also been supported by Serbian Academy of Sciences and Arts (SASA) under grant "Effects of combined stressing in modern microelectronical circuits (multistress)" (grant no. F-148.).
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