Istrazivanja i projektovanja za privreduJournal of Applied Engineering Science

Modeling of NBTI degradation in p-channel VDMOSFETs


DOI: 10.5937/jaes0-26760 
This is an open access article distributed under the CC BY 4.0
Creative Commons License

Nikola Mitrovic*
University of Nis, Faculty of Electronic Engineering, Department of Microelectronics, Nis, Serbia

Danijel Dankovic
University of Nis, Faculty of Electronic Engineering, Department of Microelectronics, Nis, Serbia

Zoran Prijic
University of Nis, Faculty of Electronic Engineering, Department of Microelectronics, Nis, Serbia

Ninoslav Stojadinovic
Serbian Academy of Sciences and Arts (SASA), Belgrade, Serbia

This paper gives insight in reliability of p-channel VDMOSFET power transistors subjected to NBT stressing. Effects that lead to degradation of characteristics of these electronic circuits are presented, out of which threshold voltage shift with NBT stressing is further analysed. Measurements have been done and experimental results of the threshold voltage degradation of power transistors IRF9520 caused by different types of negative bias temperature stressing are shown. Stressing types, both static and pulsed, and their impact on transistors, especially on threshold voltage shifts have been explained in more details. An elementary equivalent electrical circuit is designed and proposed with the goal to model impact of both types of stressing, and also to calculate and estimate reliability of the circuit under specified stress. All of the elements of the modeling circuit and their dependencies are explained. Example of modeling from the experimental data is given together with the comparison between measured and modeled results. Differences between obtained results are discussed.

View article

This work has been supported by the Ministry of Education, Science and Technological Development of the Republic of Serbia under grant "Characterization, analysis, and modeling of physical phenomena in thin layers for application in MOS nanocomponents" (grant no. OI-171026) and under grant "Design, Optimization and Application of Energy Harvesting Sensor Technologies and (grant no. TR-32026). Work has also been supported by Serbian Academy of Sciences and Arts (SASA) under grant "Effects of combined stressing in modern microelectronical circuits (multistress)" (grant no. F-148.).

1. Ogawa S., Shimaya M., Shiono N., (1995) “Interface-trap generation at ultrathin SiO2 (4–6 nm)-Si interfaces during negative-bias temperature aging”, Journal of Applied Physics, vol. 77, pp. 1137–1148.

2. Mahapatra S., Alam M.A., BharathKumar P., Dalei T.R., Varghese D., Saha D., (2005) “Negative Bias Temperature Instability in CMOS Devices“, Microelectronics Engineering, vol. 80, pp. 114-121.

3. Stojadinovic N., Dankovic D., Djoric-Veljkovic S., Davidovic V., Manic I., Golubovic S., (2005) “Negative bias temperature instability mechanisms in p-channel power VDMOSFETs”, Microelectronics Reliability, vol. 45, pp. 1343-1348.

4. Stathis J.H., Zafar S., (2006) “The negative bias temperature instability in MOS devices: A Review”, Microelectronics Reliability, vol. 46, pp. 270-286.

5. Dankovic D., Manic I., Djoric-Veljkovic S., Davidovic V., Golubovic S., Stojadinovic N., (2006) “NBT stress-induced degradation and lifetime estimation in p-channel power VDMOSFETs”, Microelectronics Reliability, vol. 46, pp. 1828-1833.

6. Reisinger H., GrasserT., Gustin W., Schlunder C., (2010) “The statistical analysis of individual defects constituting NBTI and its implications for modeling DC- and AC-stress”, IEEE International Reliability Physics Symposium, pp. 7–15.

7. Prijic A., Dankovic D., Vracar Lj., Manic I., Prijic Z., Stojadinovic N., (2012) “A method for negative bias temperature instability (NBTI) measurements on power VDMOS transistors”, Measurement Science and Technology, vol. 23.

8. Davidovic V., Dankovic D., Ilic A., Manic I., Golubovic S., Djoric-Veljkovic S., Prijic Z., Stojadinovic N., (2016) “NBTI and Irradiation Effects in P-Channel Power VDMOS Transistors”, IEEE Transactions on Nuclear Science, vol. 63, pp. 1268-1275.

9. Dankovic D., Stojadinovic N., Prijic Z., Manic I., Davidovic V., Djoric-Veljkovic S., Golubovic S., (2015) “Analysis of recoverable and permanent components of threshold voltage shift in NBT stressed pchannel power VDMOSFET”, Chinese Physics B, vol. 24.

10. Dankovic D., Manic I., Davidovic V., Prijic A., Marjanovic M., Ilic A., Prijic Z., Stojadinovic N., (2016) “On the recoverable and permanent components of NBTI in p-channel power VDMOSFETs”, IEEE Trans. Device Mater. Reliab., vol. 16, pp. 522–531.

11. Mahapatra S., Goel N., Desai S., Gupta S., Jose B., Mukhopadhyay S., Joshi K., Jain A., Islam A. E., Alam M. A., (2013) “A comparative study of different physics-based NBTI models”, IEEE Transactions on Electron Devices, vol. 60, pp. 901-916.

12. Dankovic D., Manic I., Stojadinovic N., Prijic Z., Djoric-Veljkovic S., Davidovic V., Prijic A., Paskaleva A., Spassov D., Golubovic S., (2017) “Modelling of threshold voltage shift in pulsed NBT stressed p-channel power VDMOSFETs” Proceedings in IEEE 30th International Conference on Microelectronics (MIEL), pp. 147–151.

13. Mitrovic N., Dankovic D., Prijic Z., Stojadinovic N., (2019) “Modelling of ∆VT in NBT Stressed p-channel power VDMOSFETs”, Proceedings in IEEE 31st International Conference on Microelectronics (MIEL), pp. 177–180.

14. Dankovic D., Mitrovic N., Prijic Z., Stojadinovic N., (2020) “Modeling of NBTS effects in p-channel power VDMOSFETs“, IEEE Trans. Device Mater. Reliab., vol. 20, pp. 204-213, 2020.

15. Khovanski A. G., (1998) Geometry of Differential Equations, American Mathematical Soc.